1. Field of the Invention
This invention relates generally to the field of analog-to-digital converters and more particularly this invention relates to neural network analog-to-digital converters with latched outputs for increased conversion speeds.
2. Description of the Prior Art
A wide variety of electronic circuit designs for analog to digital converters (referred to hereinafter as A/D converters) are known in the art. One particular design employs successive approximation to accomplish conversion. In this design a binary number generator is coupled to a digital-to-analog converter (referred to hereinafter as D/A converters). The output of the D/A converter is coupled to a first input of a comparator and the input analog voltage to be converted is coupled to a second input of the comparator. The output from the binary number generator changes in value until the output of the D/A converter approximately equals the input voltage. The binary number which the number generator is producing at the time this threshold is reached is considered the digital equivalent of the analog voltage. One drawback of this design is that a series of approximations must be performed which may consume a large number of clock cycles before an accurate result is achieved(n steps are required for an n-bit converter). Accordingly, this type of A/D converter is undesirably slow.
Another design which performs A/D conversions faster than successive approximation converters is a parallel flash A/D converter. In a parallel flash A/D converter, a binary digital output representative of the analog input voltage is produced in a single clock cycle. Conventional flash A/D converters employ resistor ladder networks in which a series of resistors each having similar values are connected between a reference voltage and ground to form nodes between the resistors that provide reference voltages for a plurality of comparators. The reference voltages are applied to a first input of each comparator and the analog input voltage to be converted is connected to a second input of each comparator. The output of the comparators depend on whether or not the input voltage exceeds the corresponding reference voltage. These outputs are encoded to produce a binary number having a value corresponding to the value of the analog input voltage. Although flash A/D converters are much faster than successive approximation designs, they require complex circuitry and increased power.
It is understood that in general there is a tradeoff between circuit size and speed in A/D converters. Conventional successive approximation A/D converters are relatively small in size, however, as noted they require a relatively large number of clock cycles to provide an accurate digital representation of the input analog voltage. In contrast, the flash A/D converter produces an output in essentially a single clock cycle, however, the circuitry for this design is much more complex. This design requires a resistor ladder network having 2.sup.n +1 resistors and 2.sup.n comparators for an n-bit converter in addition to a decoding network. Thus, this design requires a relatively large array of solid state devices for implementation.
Another A/D converter design is found in U.S. Pat. No. 4,987,417 invented by Buckland. In this design, the outputs from higher order comparators feed forward through a resistor network to the reference inputs of lower order comparators. This forms a neural network for performing the conversion wherein the comparison voltage for a given comparator depends on the results from higher order comparators. The adaptive referencing ability of the circuit allows fewer elements to be used in implementation of the converter, however, valid conversion results are not available until each comparator produces a stable output.
While the prior art designs have improved the speed of A/D converters and/or decreased the circuitry necessary for implementation, there remains a need in the field for fast A/D converters with high resolution and limited circuit complexity. It is therefore an object of the present invention to provide a high resolution, high speed A/D converter which employs a limited number of circuit elements.